Búsqueda de Publicación - Prisma - Unidad de Bibliometría

Búsqueda de Publicación - Prisma - Unidad de Bibliometría

Publicaciones en la fuente VLSI CIRCUITS AND SYSTEMS II, PTS 1 AND 2

Ponencia: 17

TOTAL: 17

Tipo	Año	Título	Fuente
Ponencia	2005	A 0.18 mu m CMOS low noise, highly linear continuous-time seventh-order elliptic low-pass filter	VLSI CIRCUITS AND SYSTEMS II, PTS 1 AND 2
Ponencia	2005	A 0.35 mu m CMOS 17-bit@40-kS/s cascade 2-1 Sigma Delta modulator with programmable gain and programmable chopper stabilization	VLSI CIRCUITS AND SYSTEMS II, PTS 1 AND 2
Ponencia	2005	A methodology for the characterization of arithmetic circuits on CMOS deep submicron technologies	VLSI CIRCUITS AND SYSTEMS II, PTS 1 AND 2
Ponencia	2005	A mismatch characterization and simulation environment for weak-to-strong inversion CMOS transistors	VLSI CIRCUITS AND SYSTEMS II, PTS 1 AND 2
Ponencia	2005	A reuse-based framework for the design of analog and mixed-signal ICs	VLSI CIRCUITS AND SYSTEMS II, PTS 1 AND 2
Ponencia	2005	ACE16k based stand-alone system for real-time pre-processing tasks	VLSI CIRCUITS AND SYSTEMS II, PTS 1 AND 2
Ponencia	2005	Algorithms to get the maximum operation frequency for skew-tolerant clocking schemes	VLSI CIRCUITS AND SYSTEMS II, PTS 1 AND 2
Ponencia	2005	Application of clock gating techniques at a flip-flop level to switching noise reduction in VLSI circuits	VLSI CIRCUITS AND SYSTEMS II, PTS 1 AND 2
Ponencia	2005	Continuous-time cascaded Delta Sigma modulators for VDSL: A comparative study	VLSI CIRCUITS AND SYSTEMS II, PTS 1 AND 2
Ponencia	2005	Design of a 12-bit 80MS/s CMOS digital-to-analog converter for PLC-VDSL applications	VLSI CIRCUITS AND SYSTEMS II, PTS 1 AND 2
Ponencia	2005	Design of a 12-bit 80MS/s pipeline analog-to-digital converter for PLC-VDSL applications	VLSI CIRCUITS AND SYSTEMS II, PTS 1 AND 2
Ponencia	2005	Embedded desing-for-testability strategies to test high-resolution SD modulators	VLSI CIRCUITS AND SYSTEMS II, PTS 1 AND 2
Ponencia	2005	FPGA implementation of a fuzzy based video de-interlacing algorithm	VLSI CIRCUITS AND SYSTEMS II, PTS 1 AND 2
Ponencia	2005	Geometrically-constrained, parasitic-aware synthesis of analog ICs	VLSI CIRCUITS AND SYSTEMS II, PTS 1 AND 2
Ponencia	2005	On the suitability and development of layout templates for analog layout reuse and layout-aware synthesis	VLSI CIRCUITS AND SYSTEMS II, PTS 1 AND 2
Ponencia	2005	Performance analysis of full adders in CMOS technologies	VLSI CIRCUITS AND SYSTEMS II, PTS 1 AND 2
Ponencia	2005	Simulation-based high-level synthesis of nyquist-rate data converters using MATLAB/SIMULINK	VLSI CIRCUITS AND SYSTEMS II, PTS 1 AND 2