Erica Tena Sanchez

Profesora Ayudante Doctora
etena@us.es
Área de conocimiento: Tecnología Electrónica
Departamento: Tecnología Electrónica
Grupo: DISEÑO DE CIRCUITOS INTEGRADOS DIGITALES Y MIXTOS (TIC-180)
Tipo Año Título Fuente
Artículo2022 Gate-level design methodology for side-channel resistant logic styles using TFETs IEEE Embedded Systems Letters
Artículo2022 Gate-level hardware countermeasure comparison against power analysis attacks APPLIED SCIENCES-BASEL
Artículo2022 Hardware countermeasures benchmarking against fault attacks APPLIED SCIENCES-BASEL
Artículo2021 Design and analysis of secure emerging crypto-hardware using HyperFET devices IEEE Transactions on Emerging Topics in Computing
Artículo2021 Experimental fia methodology using clock and control signal modifications under power supply and temperature variations SENSORS
Artículo2021 Trivium stream cipher countermeasures against fault injection attacks and DFA IEEE ACCESS
Ponencia2020 Hamming-code based fault detection design methodology for block ciphers Proceedings - IEEE International Symposium on Circuits and Systems
Artículo2020 Projection of dual-rail dpa countermeasures in future finfet and emerging tfet technologies ACM Journal on Emerging Technologies in Computing Systems
Ponencia2019 Benchmarking of nanometer technologies for DPA-resilient DPL-based cryptocircuits Proceedings - 33rd Conference on Design of Circuits and Integrated Systems, DCIS 2018
Artículo2019 Logic minimization and wide fan-in issues in DPL-based cryptocircuits against power analysis attacks INTERNATIONAL JOURNAL OF CIRCUIT THEORY AND APPLICATIONS
Ponencia2018 Effect of temperature variation in experimental DPA and DEMA attacks 2018 28TH INTERNATIONAL SYMPOSIUM ON POWER AND TIMING MODELING, OPTIMIZATION AND SIMULATION (PATMOS)
Artículo2017 Embedded electronic circuits for cryptography, hardware security and true random number generation: an overview INTERNATIONAL JOURNAL OF CIRCUIT THEORY AND APPLICATIONS
Artículo2017 Power and energy issues on lightweight cryptography JOURNAL OF LOW POWER ELECTRONICS
Ponencia2017 Secure cryptographic hardware implementation issues for high-performance applications Proceedings - 2016 26th International Workshop on Power and Timing Modeling, Optimization and Simulation, PATMOS 2016
Artículo2016 Application specific integrated circuit solution for multi-input multi-output piecewise-affine functions INTERNATIONAL JOURNAL OF CIRCUIT THEORY AND APPLICATIONS
Ponencia2016 Diseño de circuitos integrados y seguridad de circuitos criptográficos frente a ataques III Jornada de investigación y postgrado: Libro de Actas
Ponencia2016 Optimized DPA attack on Trivium stream cipher using correlation shape distinguishers 2015 Conference on Design of Circuits and Integrated Systems, DCIS 2015
Ponencia2015 DPA vulnerability analysis on Trivium stream cipher using an optimized power model 2015 IEEE INTERNATIONAL SYMPOSIUM ON CIRCUITS AND SYSTEMS (ISCAS)
Ponencia2015 Programmable ASICs for Model Predictive Control 2015 IEEE INTERNATIONAL CONFERENCE ON INDUSTRIAL TECHNOLOGY (ICIT)
Artículo2014 A Methodology for Optimized Design of Secure Differential Logic Gates for DPA Resistant Circuits IEEE JOURNAL ON EMERGING AND SELECTED TOPICS IN CIRCUITS AND SYSTEMS
Ponencia2014 Design and test of a low-power 90nm XOR/XNOR gate for cryptographic applications 2014 24th International Workshop on Power and Timing Modeling, Optimization and Simulation, PATMOS 2014
Ponencia2014 Low-Power Differential Logic Gates for DPA Resistant Circuits 2014 17TH EUROMICRO CONFERENCE ON DIGITAL SYSTEM DESIGN (DSD)
Artículo2013 A programmable and configurable ASIC to generate piecewise-affine functions defined over general partitions IEEE TRANSACTIONS ON CIRCUITS AND SYSTEMS I-REGULAR PAPERS
Ponencia2012 ASIC-in-the-loop methodology for verification of piecewise affine controllers 2012 19th IEEE International Conference on Electronics, Circuits and Systems (ICECS)
Ponencia2012 Reducing bit flipping problems in SRAM physical unclonable functions for chip identification 2012 19th IEEE International Conference on Electronics, Circuits and Systems (ICECS)

Proyectos de Investigación

Fecha de inicio Fecha de fin Rol Denominación Agencia financiadora
01/01/2022 31/12/2022 Investigador/a SCARoT: Side-Channel Attacks on Root of Trust / Ataques laterales sobre la Raíz de Confianza (US-1380823) Consejería de Economía, Conocimiento, Empresas y Universidad (Autonómico)
30/12/2016 29/12/2019 Investigador/a Integración y Validación en Laboratorio de Contramedidas Frente a Ataques Laterales en Criptocircuitos Microelectrónicos (TEC2016-80549-R) Ministerio de Economía y Competitividad (Nacional)
01/01/2014 30/09/2017 Investigador/a Cesar: Circuitos Microelectrónicos Seguros Frente a Ataques Laterales (TEC2013-45523-R) Ministerio de Economía y Competitividad (Nacional)
01/09/2021 31/08/2025 Investigador/a Diseño, implementación y validación en hardware de una raíz de confianza resistente a ataques, para sistemas empotrados seguros (PID2020-116664RB-I00) Ministerio de Ciencia e Innovación (Nacional)
El investigador no tiene ningún resultado de investigación asociado