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Ver Investigador - - Prisma - Unidad de Bibliometría

Pablo Saraza Canflanca

Predoctoral PIF FPI Ministerio
pablosc@us.es
Tipo Año Título Fuente
Artículo2024 Reliability improvement of SRAM PUFs based on a detailed experimental study into the stochastic effects of aging AEU-INTERNATIONAL JOURNAL OF ELECTRONICS AND COMMUNICATIONS
Ponencia2023 A detailed, cell-by-cell look into the effects of aging on an SRAM PUF using a specialized test array Proceedings - 2023 19th International Conference on Synthesis, Modeling, Analysis and Simulation Methods, and Applications to Circuit Design, SMACD 2023
Ponencia2023 Challenges and solutions to the defect-centric modeling and circuit simulation of time-dependent variability IEEE International Reliability Physics Symposium Proceedings
Artículo2022 A DRV-based bit selection method for SRAM PUF key generation and its impact on ECCs INTEGRATION-THE VLSI JOURNAL
Ponencia2022 A smart SRAM-cell array for the experimental study of variability phenomena in CMOS technologies IEEE International Reliability Physics Symposium Proceedings
Ponencia2022 A systematic approach to RTN parameter fitting based on the Maximum Current Fluctuation Proceedings - 2022 18th International Conference on Synthesis, Modeling, Analysis and Simulation Methods, and Applications to Circuit Design, SMACD 2022
Artículo2022 Determination of the time constant distribution of a defect-centric time-dependent variability model for Sub-100-nm FETs IEEE TRANSACTIONS ON ELECTRON DEVICES
Artículo2022 On the Impact of the Biasing History on the Characterization of Random Telegraph Noise IEEE TRANSACTIONS ON INSTRUMENTATION AND MEASUREMENT
Ponencia2021 A study of SRAM PUFs reliability using the static noise margin SMACD / PRIME 2021 - International Conference on Synthesis, Modeling, Analysis and Simulation Methods and Applications to Circuit Design and 16th Conference on PhD Research in Microelectronics and Electronics
Ponencia2021 Circuit reliability prediction: challenges and solutions for the device time-dependent variability characterization roadblock LAEDC 2021 - IEEE Latin America Electron Devices Conference
Ponencia2021 Dealing with hierarchical partitioning in bottom-up design methodologies SMACD / PRIME 2021 - International Conference on Synthesis, Modeling, Analysis and Simulation Methods and Applications to Circuit Design and 16th Conference on PhD Research in Microelectronics and Electronics
Artículo2021 Improving the reliability of SRAM-based PUFs under varying operation conditions and aging degradation MICROELECTRONICS RELIABILITY
Ponencia2021 Simulating the impact of random telegraph noise on integrated circuits SMACD / PRIME 2021 - International Conference on Synthesis, Modeling, Analysis and Simulation Methods and Applications to Circuit Design and 16th Conference on PhD Research in Microelectronics and Electronics
Artículo2021 Statistical characterization of time-dependent variability defects using the maximum current fluctuation IEEE TRANSACTIONS ON ELECTRON DEVICES
Artículo2021 Statistical threshold voltage shifts caused by BTI and HCI at nominal and accelerated conditions SOLID-STATE ELECTRONICS
Artículo2021 Unified RTN and BTI statistical compact modeling from a defect-centric perspective SOLID-STATE ELECTRONICS
Artículo2020 A robust and automated methodology for the analysis of Time-Dependent Variability at transistor level INTEGRATION-THE VLSI JOURNAL
Artículo2020 Flexible Setup for the Measurement of CMOS Time-Dependent Variability with Array-Based Integrated Circuits IEEE TRANSACTIONS ON INSTRUMENTATION AND MEASUREMENT
Ponencia2020 Improving the reliability of SRAM-based PUFs in the presence of aging Proceedings - 2020 15th IEEE International Conference on Design and Technology of Integrated Systems in Nanoscale Era, DTIS 2020
Artículo2020 Modeling of variability and reliability in analog circuits Modelling methodologies in analogue integrated circuit design
Artículo2019 A detailed study of the gate/drain voltage dependence of RTN in bulk pMOS transistors MICROELECTRONIC ENGINEERING
Ponencia2019 A New Time Efficient Methodology for the Massive Characterization of RTN in CMOS Devices 2019 IEEE INTERNATIONAL RELIABILITY PHYSICS SYMPOSIUM (IRPS)
Ponencia2019 Generation of Lifetime-Aware Pareto-Optimal Fronts Using a Stochastic Reliability Simulator Design Automation and Test in Europe Conference and Exhibition
Ponencia2019 New method for the automated massive characterization of Bias Temperature Instability in CMOS transistors Design Automation and Test in Europe Conference and Exhibition
Ponencia2019 TiDeVa: A Toolbox for the Automated and Robust Analysis of Time-Dependent Variability at Transistor Level SMACD 2019 - 16th International Conference on Synthesis, Modeling, Analysis and Simulation Methods and Applications to Circuit Design, Proceedings
Ponencia2018 A Model Parameter Extraction Methodology Including Time-Dependent Variability for Circuit Reliability Simulation SMACD 2018 - 15th International Conference on Synthesis, Modeling, Analysis and Simulation Methods and Applications to Circuit Design
Ponencia2018 Automated Massive RTN Characterization Using a Transistor Array Chip SMACD 2018 - 15th International Conference on Synthesis, Modeling, Analysis and Simulation Methods and Applications to Circuit Design
Ponencia2018 Design considerations of an SRAM array for the statistical validation of time-dependent variability models SMACD 2018 - 15th International Conference on Synthesis, Modeling, Analysis and Simulation Methods and Applications to Circuit Design
Study of variability phenomena on CMOS technologies for its mitigation and exploitation (2021)
Dirigida por: Fernandez Fernandez, Francisco Vidal, Castro López, Rafael
Este investigador no ha dirigido/tutorizado tesis

Proyectos de Investigación

Fecha de inicio Fecha de fin Rol Denominación Agencia financiadora
01/09/2023 31/08/2027 Investigador/a Fiabilidad, seguridad y eficiencia energética en dispositivos y circuitos electrónicos para IoT edge (TIRELESS-IMSE) (PID2022-136949OB-C21) Ministerio de Ciencia e Innovación (Nacional)
01/06/2020 29/02/2024 Investigador/a The Variability Challenge in Nano-CMOS: from Device Modeling to IC Design for Mitigation and Exploitation (Vigilant-Imse) (PID2019-103869RB-C31) Ministerio de Ciencia, Innovación y Universidades (Nacional)
30/12/2016 29/06/2021 Investigador/a Dispositivos, Circuitos y Arquitecturas Fiables y de Bajo Consumo para Iot (TEC2016-75151-C3-3-R) Ministerio de Economía y Competitividad (Nacional)
30/12/2016 29/06/2021 Contratado Dispositivos, Circuitos y Arquitecturas Fiables y de Bajo Consumo para Iot (TEC2016-75151-C3-3-R) Ministerio de Economía y Competitividad (Nacional)
01/01/2014 31/12/2018 Contratado Aproximación Multinivel al Diseño Orientado a la Fiabilidad de Circuitos Integrados Analógicos y Digitales (TEC2013-45638-C3-3-R) Ministerio de Economía y Competitividad (Nacional)
El investigador no tiene ningún resultado de investigación asociado