Juan Nuñez Martinez

Tipo Año Título Fuente
Artículo2022 Gate-level design methodology for side-channel resistant logic styles using TFETs IEEE Embedded Systems Letters
Artículo2022 How frequency injection locking can train oscillatory neural networks to compute in phase IEEE TRANSACTIONS ON NEURAL NETWORKS AND LEARNING SYSTEMS
Artículo2021 Design and analysis of secure emerging crypto-hardware using HyperFET devices IEEE Transactions on Emerging Topics in Computing
Artículo2021 Digital Implementation of Oscillatory Neural Network for Image Recognition Applications FRONTIERS IN NEUROSCIENCE
Artículo2021 Insights into the dynamics of coupled VO2 oscillators for ONNs IEEE TRANSACTIONS ON CIRCUITS AND SYSTEMS II-EXPRESS BRIEFS
Artículo2021 Oscillatory neural networks using VO2 based phase encoded logic FRONTIERS IN NEUROSCIENCE
Ponencia2020 An approach to the device-circuit co-design of HyperFeT circuits Proceedings - IEEE International Symposium on Circuits and Systems
Artículo2020 Approaching the design of energy recovery logic circuits using TFETs IEEE TRANSACTIONS ON NANOTECHNOLOGY
Artículo2020 Hybrid phase transition FET devices for logic computation IEEE Journal on Exploratory Solid-State Computational Devices and Circuits
Artículo2020 Phase transition device for phase storing IEEE TRANSACTIONS ON NANOTECHNOLOGY
Artículo2020 Projection of dual-rail dpa countermeasures in future finfet and emerging tfet technologies ACM Journal on Emerging Technologies in Computing Systems
Ponencia2019 An IC array for the statistical characterization of time-dependent variability of basic circuit blocks SMACD 2019 - 16th International Conference on Synthesis, Modeling, Analysis and Simulation Methods and Applications to Circuit Design, Proceedings
Ponencia2019 Benchmarking of nanometer technologies for DPA-resilient DPL-based cryptocircuits Proceedings - 33rd Conference on Design of Circuits and Integrated Systems, DCIS 2018
Ponencia2019 Experimental characterization of time-dependent variability in ring oscillators SMACD 2019 - 16th International Conference on Synthesis, Modeling, Analysis and Simulation Methods and Applications to Circuit Design, Proceedings
Artículo2019 Power and speed evaluation of hyper-FET circuits IEEE ACCESS
Ponencia2018 All-inversion region g m /I D methodology for RF circuits in FinFET technologies 2018 16th IEEE International New Circuits and Systems Conference, NEWCAS 2018
Ponencia2018 Design considerations of an SRAM array for the statistical validation of time-dependent variability models SMACD 2018 - 15th International Conference on Synthesis, Modeling, Analysis and Simulation Methods and Applications to Circuit Design
Ponencia2018 Impact of TFET reverse currents into circuit operation: a case study 2018 Joint International EUROSOI Workshop and International Conference on Ultimate Integration on Silicon, EUROSOI-ULIS 2018
Artículo2018 Impact of the RT-level architecture on the power performance of tunnel transistor circuits INTERNATIONAL JOURNAL OF CIRCUIT THEORY AND APPLICATIONS
Ponencia2018 Inverting versus non-inverting dynamic logic for two-phase latch-free nanopipelines SMACD 2018 - 15th International Conference on Synthesis, Modeling, Analysis and Simulation Methods and Applications to Circuit Design
Artículo2018 Phase transition FETs for improved dynamic logic gates IEEE ELECTRON DEVICE LETTERS
Artículo2017 Comparison of TFETs and CMOS using optimal design points for power-speed tradeoffs IEEE TRANSACTIONS ON NANOTECHNOLOGY
Ponencia2017 Complementary tunnel gate topology to reduce crosstalk effects 2016 Conference on Design of Circuits and Integrated Systems, DCIS 2016 - Proceedings
Ponencia2017 Exploring logic architectures suitable for TFETs devices Proceedings - IEEE International Symposium on Circuits and Systems
Ponencia2017 Impact of pipeline in the power performance of tunnel transistor circuits Proceedings - 2016 26th International Workshop on Power and Timing Modeling, Optimization and Simulation, PATMOS 2016
Artículo2017 Insights Into the operation of hyper-FET-based circuits IEEE TRANSACTIONS ON ELECTRON DEVICES
Artículo2017 Reducing the impact of reverse currents in tunnel FET rectifiers for energy harvesting applications IEEE JOURNAL OF THE ELECTRON DEVICES SOCIETY
Ponencia2017 Secure cryptographic hardware implementation issues for high-performance applications Proceedings - 2016 26th International Workshop on Power and Timing Modeling, Optimization and Simulation, PATMOS 2016
Ponencia2016 Assessing application areas for tunnel transistor technologies 2015 Conference on Design of Circuits and Integrated Systems, DCIS 2015
Artículo2016 Comparative analysis of projected tunnel and CMOS transistors for different logic application areas IEEE TRANSACTIONS ON ELECTRON DEVICES
Artículo2016 Design methodology for low-jitter differential clock recovery circuits in high performance ADCs ANALOG INTEGRATED CIRCUITS AND SIGNAL PROCESSING
Ponencia2016 Improving robustness of dynamic logic based pipelines 2015 Conference on Design of Circuits and Integrated Systems, DCIS 2015
Ponencia2016 Low-jitter differential clock driver circuits for high-performance high-resolution ADCs 2015 Conference on Design of Circuits and Integrated Systems, DCIS 2015
Ponencia2015 An approach to the design of low-jitter differential clock recovery circuits for high performance ADCs 2015 IEEE 6TH LATIN AMERICAN SYMPOSIUM ON CIRCUITS & SYSTEMS (LASCAS)
Artículo2015 Improving speed of tunnel FETs logic circuits ELECTRONICS LETTERS
Ponencia2014 DOE based high-performance gate-level pipelines 2014 24th International Workshop on Power and Timing Modeling, Optimization and Simulation, PATMOS 2014
Artículo2014 Experimental Validation of a Two-Phase Clock Scheme for Fine-Grained Pipelined Circuits Based on Monostable to Bistable Logic Elements IEEE TRANSACTIONS ON VERY LARGE SCALE INTEGRATION (VLSI) SYSTEMS
Ponencia2013 Novel dynamic gate topology for superpipelines in DSM technologies 16TH EUROMICRO CONFERENCE ON DIGITAL SYSTEM DESIGN (DSD 2013)
Artículo2013 Novel pipeline architectures based on Negative Differential Resistance devices MICROELECTRONICS JOURNAL
Ponencia2013 Two-phase MOBILE interconnection schemes for ultra-grain pipeline applications INTEGRATED CIRCUIT AND SYSTEM DESIGN: POWER AND TIMING MODELING, OPTIMIZATION AND SIMULATION
Ponencia2012 Bifurcation diagrams in MOS-NDR frequency divider circuits 2012 19th IEEE International Conference on Electronics, Circuits and Systems (ICECS)
Ponencia2012 Compact and power efficient MOS-NDR Muller C-elements TECHNOLOGICAL INNOVATION FOR VALUE CREATION
Artículo2012 Domino inspired MOBILE networks ELECTRONICS LETTERS
Artículo2012 Two-phase RTD-CMOS pipelined circuits IEEE TRANSACTIONS ON NANOTECHNOLOGY
Ponencia2011 Efficient realization of RTD-CMOS logic gates Proceedings of the ACM Great Lakes Symposium on VLSI, GLSVLSI
Ponencia2011 Evaluation of MOBILE-based gate-level pipelining augmenting CMOS with RTDs VLSI CIRCUITS AND SYSTEMS V
Artículo2011 RTD-CMOS pipelined networks for reduced power consumption IEEE TRANSACTIONS ON NANOTECHNOLOGY
Artículo2011 Simplified single-phase clock scheme for MOBILE networks ELECTRONICS LETTERS
Ponencia2010 Evaluation of RTD-CMOS logic gates 13TH EUROMICRO CONFERENCE ON DIGITAL SYSTEM DESIGN: ARCHITECTURES, METHODS AND TOOLS
Ponencia2010 Single phase MOS-NDR MOBILE networks 2010 IEEE INTERNATIONAL SYMPOSIUM ON CIRCUITS AND SYSTEMS
Artículo2009 Efficient realisation of MOS-NDR threshold logic gates ELECTRONICS LETTERS
Ponencia2009 Fast and area efficient multi-input Muller C-element based on MOS-NDR ISCAS: 2009 IEEE INTERNATIONAL SYMPOSIUM ON CIRCUITS AND SYSTEMS, VOLS 1-5
Artículo2009 Operation limits for RTD-based MOBILE circuits IEEE TRANSACTIONS ON CIRCUITS AND SYSTEMS I-REGULAR PAPERS
Ponencia2008 Design of RTD-based NMIN/NMAX gates 2008 8th IEEE Conference on Nanotechnology, IEEE-NANO
Ponencia2008 Limits to a correct operation in RTD-based ternary inverters PROCEEDINGS OF 2008 IEEE INTERNATIONAL SYMPOSIUM ON CIRCUITS AND SYSTEMS, VOLS 1-10
Ponencia2007 A quasi-differential quantizer based on SMOBILE SBCCI2007: 20TH SYMPOSIUM ON INTEGRATED CIRCUITS AND SYSTEMS DESIGN
Ponencia2007 Correct DC operation in RTD-based ternary inverters 2007 2ND IEEE INTERNATIONAL CONFERENCE ON NANO/MICRO ENGINEERED AND MOLECULAR SYSTEMS, VOLS 1-3
Ponencia2007 Correct operation in SMOBILE-based quasi-differential quantizers 2007 EUROPEAN CONFERENCE ON CIRCUIT THEORY AND DESIGN, VOLS 1-3
Ponencia2007 Holding preserving in RTD-based multiple-valued quantizers 2007 7TH IEEE CONFERENCE ON NANOTECHNOLOGY, VOL 1-3
Ponencia2007 Limits to a correct evaluation in RTD-based ternary inverters 2006 13TH IEEE INTERNATIONAL CONFERENCE ON ELECTRONICS, CIRCUITS AND SYSTEMS, VOLS 1-3
Ponencia2006 DC correct operation in MOBILE inverters IEEE MWSCAS'06: PROCEEDINGS OF THE 2006 49TH MIDWEST SYMPOSIUM ON CIRCUITS AND SYSTEMS, VOL II
Ponencia2006 Design guides for a correct DC operation in RTD-based threshold gates DSD 2006: 9TH EUROMICRO CONFERENCE ON DIGITAL SYSTEM DESIGN: ARCHITECTURES, METHODS AND TOOLS, PROCEEDINGS
Ponencia2006 Limits to a correct evaluation in RTD-based ternary inverters Proceedings of the IEEE International Conference on Electronics, Circuits, and Systems
Ponencia2006 Operation limits for MOBILE followers 2006 6th IEEE Conference on Nanotechnology, IEEE-NANO 2006

Proyectos de Investigación

Fecha de inicio Fecha de fin Rol Denominación Agencia financiadora
01/01/2011 31/12/2014 Investigador/a Arquitecturas y Circuitos con Rtds para Aplicaciones Lógicas y no Lineales (TEC2010-18937) Ministerio de Ciencia e Innovación (Nacional)
31/01/2008 31/12/2012 Investigador/a Diseño e implementación de circuitos multivaluados usando dispositivos con característica Ndr (P07-TIC-02961) Junta de Andalucía - Consejería de Innovación, Ciencia y Empresas (Autonómico)
01/01/2022 31/12/2022 Responsable Power, reliability and security challenges in advanced CMOS and beyond-CMOS devices and circuits (RESURGENCE) (US-1380876) Consejería de Economía, Conocimiento, Empresas y Universidad (Autonómico)
01/03/2006 28/02/2009 Investigador/a Técnicas de diseño y test de circuitos integrados mixtos en tecnologías emergentes (EXC/2005/TIC-927) Junta de Andalucía (Plan Andaluz de Investigación) (Autonómico)
01/01/2018 30/06/2021 Investigador/a Circuitos y Arquitecturas con Dispositivos Steep Slope para Aplicaciones de muy Bajo Consumo de Potencia (TEC2017-87052-P) Ministerio de Economía y Competitividad (Nacional)
01/01/2014 30/06/2018 Investigador/a Nano-Arquitecturas para Computación Lógica Usando Dispositivos Emergentes (TEC2013-40670-P) Ministerio de Economía y Competitividad (Nacional)
El investigador no tiene ningún resultado de investigación asociado