| Ponencia | 2023 |
Characterizing BTI and HCD in 1.2V 65nm CMOS Oscillators made from Combinational Standard Cells and Processor Logic Paths
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IEEE International Reliability Physics Symposium Proceedings |
| Artículo | 2023 |
Experimental demonstration of coupled differential oscillator networks for versatile applications
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FRONTIERS IN NEUROSCIENCE |
| Ponencia | 2023 |
Exploitation of Subharmonic Injection Locking for Solving Combinatorial Optimization Problems with Coupled Oscillators using VO2based devices
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Proceedings - 2023 19th International Conference on Synthesis, Modeling, Analysis and Simulation Methods, and Applications to Circuit Design, SMACD 2023 |
| Artículo | 2023 |
Learning algorithms for oscillatory neural networks as associative memory for pattern recognition
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FRONTIERS IN NEUROSCIENCE |
| Artículo | 2023 |
Operating Coupled VO-Based Oscillators for Solving Ising Models
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IEEE JOURNAL ON EMERGING AND SELECTED TOPICS IN CIRCUITS AND SYSTEMS |
| Ponencia | 2023 |
Reliability evaluation of IC Ring Oscillator PUFs
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Proceedings - 2023 19th International Conference on Synthesis, Modeling, Analysis and Simulation Methods, and Applications to Circuit Design, SMACD 2023 |
| Ponencia | 2022 |
Enhancing storage capabilities of oscillatory neural networks as associative memory
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DCIS 2022 - Proceedings of the 37th Conference on Design of Circuits and Integrated Systems |
| Artículo | 2022 |
Finite-dimensional Zinbiel algebras and combinatorial structures
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ANALELE STIINTIFICE ALE UNIVERSITATII OVIDIUS CONSTANTA-SERIA MATEMATICA |
| Artículo | 2022 |
Gate-level design methodology for side-channel resistant logic styles using TFETs
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IEEE Embedded Systems Letters |
| Artículo | 2022 |
How frequency injection locking can train oscillatory neural networks to compute in phase
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IEEE TRANSACTIONS ON NEURAL NETWORKS AND LEARNING SYSTEMS |
| Ponencia | 2022 |
Mitigating the impact of variability in NCFET-based coupled-oscillator networks applications
|
ICECS 2022 - 29th IEEE International Conference on Electronics, Circuits and Systems, Proceedings |
| Artículo | 2022 |
Spontaneous rupture and upper gastrointestinal bleeding of solid pseudopapillary neoplasm of the pancreas
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JOURNAL OF SURGICAL CASE REPORTS |
| Artículo | 2021 |
Design and analysis of secure emerging crypto-hardware using HyperFET devices
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IEEE Transactions on Emerging Topics in Computing |
| Artículo | 2021 |
Digital implementation of oscillatory neural network for image recognition applications
|
FRONTIERS IN NEUROSCIENCE |
| Artículo | 2021 |
Insights into the dynamics of coupled VO2 oscillators for ONNs
|
IEEE TRANSACTIONS ON CIRCUITS AND SYSTEMS II-EXPRESS BRIEFS |
| Artículo | 2021 |
Oscillatory neural networks using VO2 based phase encoded logic
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FRONTIERS IN NEUROSCIENCE |
| Ponencia | 2020 |
An approach to the device-circuit co-design of HyperFeT circuits
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Proceedings - IEEE International Symposium on Circuits and Systems |
| Artículo | 2020 |
Approaching the design of energy recovery logic circuits using TFETs
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IEEE TRANSACTIONS ON NANOTECHNOLOGY |
| Artículo | 2020 |
Hybrid phase transition FET devices for logic computation
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IEEE Journal on Exploratory Solid-State Computational Devices and Circuits |
| Artículo | 2020 |
Phase transition device for phase storing
|
IEEE TRANSACTIONS ON NANOTECHNOLOGY |
| Artículo | 2020 |
Projection of dual-rail dpa countermeasures in future finfet and emerging tfet technologies
|
ACM Journal on Emerging Technologies in Computing Systems |
| Ponencia | 2019 |
An IC array for the statistical characterization of time-dependent variability of basic circuit blocks
|
SMACD 2019 - 16th International Conference on Synthesis, Modeling, Analysis and Simulation Methods and Applications to Circuit Design, Proceedings |
| Ponencia | 2019 |
Benchmarking of nanometer technologies for DPA-resilient DPL-based cryptocircuits
|
Proceedings - 33rd Conference on Design of Circuits and Integrated Systems, DCIS 2018 |
| Ponencia | 2019 |
Experimental characterization of time-dependent variability in ring oscillators
|
SMACD 2019 - 16th International Conference on Synthesis, Modeling, Analysis and Simulation Methods and Applications to Circuit Design, Proceedings |
| Artículo | 2019 |
Power and speed evaluation of hyper-FET circuits
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IEEE ACCESS |
| Ponencia | 2018 |
All-inversion region g m /I D methodology for RF circuits in FinFET technologies
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2018 16th IEEE International New Circuits and Systems Conference, NEWCAS 2018 |
| Ponencia | 2018 |
Design considerations of an SRAM array for the statistical validation of time-dependent variability models
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SMACD 2018 - 15th International Conference on Synthesis, Modeling, Analysis and Simulation Methods and Applications to Circuit Design |
| Ponencia | 2018 |
Impact of TFET reverse currents into circuit operation: a case study
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2018 Joint International EUROSOI Workshop and International Conference on Ultimate Integration on Silicon, EUROSOI-ULIS 2018 |
| Artículo | 2018 |
Impact of the RT-level architecture on the power performance of tunnel transistor circuits
|
INTERNATIONAL JOURNAL OF CIRCUIT THEORY AND APPLICATIONS |
| Ponencia | 2018 |
Inverting versus non-inverting dynamic logic for two-phase latch-free nanopipelines
|
SMACD 2018 - 15th International Conference on Synthesis, Modeling, Analysis and Simulation Methods and Applications to Circuit Design |
| Artículo | 2018 |
Phase transition FETs for improved dynamic logic gates
|
IEEE ELECTRON DEVICE LETTERS |
| Artículo | 2017 |
Comparison of TFETs and CMOS using optimal design points for power-speed tradeoffs
|
IEEE TRANSACTIONS ON NANOTECHNOLOGY |
| Ponencia | 2017 |
Complementary tunnel gate topology to reduce crosstalk effects
|
2016 Conference on Design of Circuits and Integrated Systems, DCIS 2016 - Proceedings |
| Ponencia | 2017 |
Exploring logic architectures suitable for TFETs devices
|
Proceedings - IEEE International Symposium on Circuits and Systems |
| Ponencia | 2017 |
Impact of pipeline in the power performance of tunnel transistor circuits
|
Proceedings - 2016 26th International Workshop on Power and Timing Modeling, Optimization and Simulation, PATMOS 2016 |
| Artículo | 2017 |
Insights Into the operation of hyper-FET-based circuits
|
IEEE TRANSACTIONS ON ELECTRON DEVICES |
| Artículo | 2017 |
Reducing the impact of reverse currents in tunnel FET rectifiers for energy harvesting applications
|
IEEE JOURNAL OF THE ELECTRON DEVICES SOCIETY |
| Ponencia | 2017 |
Secure cryptographic hardware implementation issues for high-performance applications
|
Proceedings - 2016 26th International Workshop on Power and Timing Modeling, Optimization and Simulation, PATMOS 2016 |
| Ponencia | 2016 |
Assessing application areas for tunnel transistor technologies
|
2015 Conference on Design of Circuits and Integrated Systems, DCIS 2015 |
| Artículo | 2016 |
Comparative analysis of projected tunnel and CMOS transistors for different logic application areas
|
IEEE TRANSACTIONS ON ELECTRON DEVICES |
| Artículo | 2016 |
Design methodology for low-jitter differential clock recovery circuits in high performance ADCs
|
ANALOG INTEGRATED CIRCUITS AND SIGNAL PROCESSING |
| Ponencia | 2016 |
Improving robustness of dynamic logic based pipelines
|
2015 Conference on Design of Circuits and Integrated Systems, DCIS 2015 |
| Ponencia | 2016 |
Low-jitter differential clock driver circuits for high-performance high-resolution ADCs
|
2015 Conference on Design of Circuits and Integrated Systems, DCIS 2015 |
| Ponencia | 2015 |
An approach to the design of low-jitter differential clock recovery circuits for high performance ADCs
|
2015 IEEE 6TH LATIN AMERICAN SYMPOSIUM ON CIRCUITS & SYSTEMS (LASCAS) |
| Artículo | 2015 |
Improving speed of tunnel FETs logic circuits
|
ELECTRONICS LETTERS |
| Ponencia | 2014 |
DOE based high-performance gate-level pipelines
|
2014 24th International Workshop on Power and Timing Modeling, Optimization and Simulation, PATMOS 2014 |
| Artículo | 2014 |
Experimental validation of a two-phase clock scheme for fine-grained pipelined circuits based on monostable to bistable logic elements
|
IEEE TRANSACTIONS ON VERY LARGE SCALE INTEGRATION (VLSI) SYSTEMS |
| Ponencia | 2013 |
Novel dynamic gate topology for superpipelines in DSM technologies
|
16TH EUROMICRO CONFERENCE ON DIGITAL SYSTEM DESIGN (DSD 2013) |
| Artículo | 2013 |
Novel pipeline architectures based on Negative Differential Resistance devices
|
MICROELECTRONICS JOURNAL |
| Ponencia | 2013 |
Two-phase MOBILE interconnection schemes for ultra-grain pipeline applications
|
INTEGRATED CIRCUIT AND SYSTEM DESIGN: POWER AND TIMING MODELING, OPTIMIZATION AND SIMULATION |
| Ponencia | 2012 |
Bifurcation diagrams in MOS-NDR frequency divider circuits
|
2012 19th IEEE International Conference on Electronics, Circuits and Systems (ICECS) |
| Ponencia | 2012 |
Compact and power efficient MOS-NDR Muller C-elements
|
TECHNOLOGICAL INNOVATION FOR VALUE CREATION |
| Artículo | 2012 |
Domino inspired MOBILE networks
|
ELECTRONICS LETTERS |
| Artículo | 2012 |
Two-phase RTD-CMOS pipelined circuits
|
IEEE TRANSACTIONS ON NANOTECHNOLOGY |
| Ponencia | 2011 |
Efficient realization of RTD-CMOS logic gates
|
Proceedings of the ACM Great Lakes Symposium on VLSI, GLSVLSI |
| Ponencia | 2011 |
Evaluation of MOBILE-based gate-level pipelining augmenting CMOS with RTDs
|
VLSI CIRCUITS AND SYSTEMS V |
| Artículo | 2011 |
RTD-CMOS pipelined networks for reduced power consumption
|
IEEE TRANSACTIONS ON NANOTECHNOLOGY |
| Artículo | 2011 |
Simplified single-phase clock scheme for MOBILE networks
|
ELECTRONICS LETTERS |
| Ponencia | 2010 |
Evaluation of RTD-CMOS logic gates
|
13TH EUROMICRO CONFERENCE ON DIGITAL SYSTEM DESIGN: ARCHITECTURES, METHODS AND TOOLS |
| Ponencia | 2010 |
Redes MOBILE MOS-NDR operando con reloj de una fase
|
XVI Workshop Iberchip (2010), p 1-4 |
| Ponencia | 2010 |
Single phase MOS-NDR MOBILE networks
|
2010 IEEE INTERNATIONAL SYMPOSIUM ON CIRCUITS AND SYSTEMS |
| Artículo | 2009 |
Efficient realisation of MOS-NDR threshold logic gates
|
ELECTRONICS LETTERS |
| Ponencia | 2009 |
Fast and area efficient multi-input Muller C-element based on MOS-NDR
|
ISCAS: 2009 IEEE INTERNATIONAL SYMPOSIUM ON CIRCUITS AND SYSTEMS, VOLS 1-5 |
| Artículo | 2009 |
Operation limits for RTD-based MOBILE circuits
|
IEEE TRANSACTIONS ON CIRCUITS AND SYSTEMS I-REGULAR PAPERS |
| Ponencia | 2008 |
Design of RTD-based NMIN/NMAX gates
|
2008 8th IEEE Conference on Nanotechnology, IEEE-NANO |
| Ponencia | 2008 |
Limits to a correct operation in RTD-based ternary inverters
|
PROCEEDINGS OF 2008 IEEE INTERNATIONAL SYMPOSIUM ON CIRCUITS AND SYSTEMS, VOLS 1-10 |
| Ponencia | 2007 |
A quasi-differential quantizer based on SMOBILE
|
SBCCI2007: 20TH SYMPOSIUM ON INTEGRATED CIRCUITS AND SYSTEMS DESIGN |
| Ponencia | 2007 |
Correct DC operation in RTD-based ternary inverters
|
2007 2ND IEEE INTERNATIONAL CONFERENCE ON NANO/MICRO ENGINEERED AND MOLECULAR SYSTEMS, VOLS 1-3 |
| Ponencia | 2007 |
Correct operation in SMOBILE-based quasi-differential quantizers
|
2007 EUROPEAN CONFERENCE ON CIRCUIT THEORY AND DESIGN, VOLS 1-3 |
| Ponencia | 2007 |
Holding Dissapearance in RTD-based Quantizers
|
European Nano Systems Worshop (2007) |
| Ponencia | 2007 |
Holding preserving in RTD-based multiple-valued quantizers
|
2007 7TH IEEE CONFERENCE ON NANOTECHNOLOGY, VOL 1-3 |
| Ponencia | 2007 |
Limits to a correct evaluation in RTD-based ternary inverters
|
2006 13TH IEEE INTERNATIONAL CONFERENCE ON ELECTRONICS, CIRCUITS AND SYSTEMS, VOLS 1-3 |
| Ponencia | 2006 |
DC correct operation in MOBILE inverters
|
IEEE MWSCAS'06: PROCEEDINGS OF THE 2006 49TH MIDWEST SYMPOSIUM ON CIRCUITS AND SYSTEMS, VOL II |
| Ponencia | 2006 |
Design guides for a correct DC operation in RTD-based threshold gates
|
DSD 2006: 9TH EUROMICRO CONFERENCE ON DIGITAL SYSTEM DESIGN: ARCHITECTURES, METHODS AND TOOLS, PROCEEDINGS |
| Ponencia | 2006 |
Limits to a correct evaluation in RTD-based ternary inverters
|
Proceedings of the IEEE International Conference on Electronics, Circuits, and Systems |
| Ponencia | 2006 |
Operation limits for MOBILE followers
|
2006 6th IEEE Conference on Nanotechnology, IEEE-NANO 2006 |
