María del Pilar Parra Fernández

Profesora Titular de Universidad
pparra@us.es
Área de conocimiento: Tecnología Electrónica
Departamento: Tecnología Electrónica
Grupo: DISEÑO DE CIRCUITOS INTEGRADOS DIGITALES Y MIXTOS (TIC-180)
Tipo Año Título Fuente
Artículo2020 An Academic Approach to FPGA Design Based on a Distance Meter Circuit IEEE REVISTA IBEROAMERICANA DE TECNOLOGIAS DEL APRENDIZAJE-IEEE RITA
Artículo2020 Breaking trivium stream cipher implemented in asic using experimental attacks and dfa SENSORS
Ponencia2019 Floorplanning as a practical countermeasure against clock fault attack in Trivium stream cipher Proceedings - 33rd Conference on Design of Circuits and Integrated Systems, DCIS 2018
Ponencia2018 Distance measurement as a practical example of FPGA design 2018 XIII TECHNOLOGIES APPLIED TO ELECTRONICS TEACHING CONFERENCE (TAEE)
Ponencia2018 Ejemplo de diseño FPGA para medidas de máximas frecuencias de operación Tecnología, Aprendizaje y Enseñanza de la Electrónica : Actas del XIII Congreso de Tecnología, Aprendizaje y Enseñanzade la Electrónica, Tenerife, 20-22 de junio, 2018
Ponencia2018 Floorplanning as a practical countermeasure against clock fault attack in Trivium stream cipher 2018 XXXIII CONFERENCE ON DESIGN OF CIRCUITS AND INTEGRATED SYSTEMS (DCIS)
Ponencia2018 FPGA design example for maximum operating frequency measurements 2018 XIII TECHNOLOGIES APPLIED TO ELECTRONICS TEACHING CONFERENCE (TAEE)
Ponencia2018 Medición de distancias como ejemplo práctico de diseño en FPGAs Tecnología, Aprendizaje y Enseñanza de la Electrónica : Actas del XIII Congreso de Tecnología, Aprendizaje y Enseñanzade la Electrónica, Tenerife, 20-22 de junio, 2018
Ponencia2016 Creating helping posters for electronic labs Proceedings of 2016 Technologies Applied to Electronics Teaching, TAEE 2016
Ponencia2016 Educational applications of a pico-processor design Proceedings of 2016 Technologies Applied to Electronics Teaching, TAEE 2016
Ponencia2010 An Improved Differential Pull-down Network Logic Configuration for DPA Resistant Circuits 2010 INTERNATIONAL CONFERENCE ON MICROELECTRONICS
Ponencia2010 Optimization of clock-gating Structures for low-leakage high-performance Applications 2010 IEEE INTERNATIONAL SYMPOSIUM ON CIRCUITS AND SYSTEMS
Ponencia2010 Switching noise optimization in the wake-up phase of leakage-aware power gating structures INTEGRATED CIRCUIT AND SYSTEM DESIGN: POWER AND TIMING MODELING, OPTIMIZATION AND SIMULATION
Ponencia2007 A methodology for switching noise estimation at gate level VLSI CIRCUITS AND SYSTEMS III
Ponencia2007 A switching noise vision of the optimization techniques for low-power synthesis 2007 EUROPEAN CONFERENCE ON CIRCUIT THEORY AND DESIGN, VOLS 1-3
Ponencia2007 Effects of buffer insertion on the average/peak power ratio in CMOS VLSI digital circuits VLSI CIRCUITS AND SYSTEMS III
Artículo2006 Optimization of master-slave flip-flops for high-performance applications INTEGRATED CIRCUIT AND SYSTEM DESIGN: POWER AND TIMING MODELING, OPTIMIZATION AND SIMULATION
Ponencia2005 Application of clock gating techniques at a flip-flop level to switching noise reduction in VLSI circuits VLSI CIRCUITS AND SYSTEMS II, PTS 1 AND 2
Ponencia2005 Performance analysis of full adders in CMOS technologies VLSI CIRCUITS AND SYSTEMS II, PTS 1 AND 2
Artículo2005 Selective Clock-Gating for Low-Power Synchronous Counters JOURNAL OF LOW POWER ELECTRONICS
Artículo2003 A new hybrid CBL-CMOS cell for optimum noise/power application INTEGRATED CIRCUIT AND SYSTEM DESIGN
Ponencia2003 Analysis of current-mode flip-flops in CMOS technologies VLSI CIRCUITS AND SYSTEMS
Ponencia2003 Switching noise reduction in clock distribution in mixed-mode VLSI circuits VLSI CIRCUITS AND SYSTEMS
Artículo2002 A technique to generate CMOS VLSI flip-flops based on differential latches Lecture Notes in Computer Science
Artículo2002 Analysis of high-performance flip-flops for submicron mixed-signal applications ANALOG INTEGRATED CIRCUITS AND SIGNAL PROCESSING
Artículo2002 High-performance edge-triggered flip-flops using weak-branch differential latch ELECTRONICS LETTERS
Artículo2002 Selective clock-gating for low power/low noise synchronous counters Lecture Notes in Computer Science
Tesis dirigidas/tutorizadas:1
Fecha lectura Título Rol
13/07/2011 DESARROLLO Y APLICACIONES DE TÉCNICAS DE CONTROL DE CORRIENTE DE ALIMENTACIÓN EN CIRCUITOS INTEGRADOS DIGITALES CMOS Director/a