Servando Espejo Meana

Profesor Titular de Universidad
espejo@us.es
Área de conocimiento: Electrónica
Departamento: Electrónica y Electromagnetismo
Grupo: INGENIERÍA DE CIRCUITOS Y SISTEMAS MICRO/NANO-MÉTRICOS (TIC-026)
Prog. doctorado: Programa de Doctorado en Ciencias y Tecnologías Físicas (RD. 99/2011)
Tipo Año Título Fuente
Artículo2016 CMOS Rad-Hard Front-End Electronics for Precise Sensors Measurements IEEE TRANSACTIONS ON NUCLEAR SCIENCE
Artículo2015 A Front-End ASIC for a 3-D Magnetometer for Space Applications by Using Anisotropic Magnetoresistors IEEE TRANSACTIONS ON MAGNETICS
Ponencia2014 A Rad-Hard Multichannel Front-End Readout ASIC for Space Applications 2014 IEEE INTERNATIONAL WORKSHOP ON METROLOGY FOR AEROSPACE (METROAEROSPACE)
Artículo2014 Four-channel self-compensating single-slope ADC for space environments ELECTRONICS LETTERS
Ponencia2013 An adaptive approach to on-chip CMOS ramp generation for high resolution single-slope ADCs 2013 European Conference on Circuit Theory and Design, ECCTD 2013 - Proceedings
Ponencia2013 SEE characterization of the AMS 0.35 μm CMOS technology Proceedings of the European Conference on Radiation and its Effects on Components and Systems, RADECS
Ponencia2011 Radiation characterization of the austriamicrosystems 0.35 μm CMOS technology Proceedings of the European Conference on Radiation and its Effects on Components and Systems, RADECS
Ponencia2010 Image processing for surface quality control in stainless steel production lines 2010 IEEE International Conference on Imaging Systems and Techniques, IST 2010 - Proceedings
Artículo2009 New visual sensors and processors SPATIAL TEMPORAL PATTERNS FOR ACTION-ORIENTED PERCEPTION IN ROVING ROBOTS
Ponencia2009 Residual Oxides Detection and Measurement in Stainless Steel Production Lines 2009 IEEE INTERNATIONAL CONFERENCE ON COMPUTATIONAL INTELLIGENCE FOR MEASUREMENT SYSTEMS AND APPLICATIONS
Ponencia2008 The Eye-RIS CMOS vision system ANALOG CIRCUIT DESIGN
Ponencia2005 ACE16k based stand-alone system for real-time pre-processing tasks VLSI CIRCUITS AND SYSTEMS II, PTS 1 AND 2
Artículo2004 A 1000 FPS at 128 x 128 vision processor with 8-Bit digitized I/O IEEE JOURNAL OF SOLID-STATE CIRCUITS
Artículo2004 ACE16k: The third generation of mixed-signal SIMD-CNN ACE chips toward VSoCs IEEE TRANSACTIONS ON CIRCUITS AND SYSTEMS I-REGULAR PAPERS
Artículo2004 Second-order neural core for bioinspired focal-plane dynamic image processing in CMOS IEEE TRANSACTIONS ON CIRCUITS AND SYSTEMS I-REGULAR PAPERS
Ponencia2003 A 1000FPS@128x128 vision processor with 8-bit digitized I/O ESSCIRC 2003: PROCEEDINGS OF THE 29TH EUROPEAN SOLID-STATE CIRCUITS CONFERENCE
Artículo2003 A bio-inspired two-layer mixed-signal flexible programmable chip for early vision IEEE TRANSACTIONS ON NEURAL NETWORKS
Ponencia2003 A mixed-signal early vision chip with embedded image and programming memories and digital I/O VLSI CIRCUITS AND SYSTEMS
Ponencia2003 A versatile sensor interface for programmable vision systems-on-chip SENSORS AND CAMERA SYSTEMS FOR SCIENTIFIC, INDUSTRIAL, AND DIGITAL PHOTOGRAPHY APPLICATIONS IV
Artículo2003 ACE16K: A 128×128 focal plane analog processor with digital I/O International Journal of Neural Systems
Artículo2003 An improved elementary processing unit for high-density CNN-based mixed-signal microprocessors for vision JOURNAL OF CIRCUITS SYSTEMS AND COMPUTERS
Ponencia2003 Analog weight buffering strategy for CNN chips Proceedings - IEEE International Symposium on Circuits and Systems
Artículo2003 CMOS realization of a 2-layer cnn universal machine chip International Journal of Neural Systems
Artículo2003 Mismatch-induced trade-offs and scalability of analog preprocessing visual microprocessor chips ANALOG INTEGRATED CIRCUITS AND SIGNAL PROCESSING
Ponencia2003 Programmable retinal dynamics in a CMOS mixed-signal array processor chip BIOENGINEERED AND BIOINSPIRED SYSTEMS
Ponencia2003 Retinal processing emulation in a programmable 2-layer analog array processor CMOS Chip Advances in Neural Information Processing Systems
Ponencia2002 A CMOS analog parallel array processor chip with programmable dynamics for early vision tasks European Solid-State Circuits Conference
Ponencia2002 A multimode gray-scale CMOS optical sensor for Visual computers. CELLULAR NEURAL NETWORKS AND THEIR APPLICATIONS
Ponencia2002 A processing element architecture for high-density focal plane analog programmable array processors Proceedings - IEEE International Symposium on Circuits and Systems
Ponencia2002 ACE16K: A 128×128 focal plane analog processor with digital I/O Proceedings of the IEEE International Workshop on Cellular Neural Networks and their Applications
Artículo2002 ACE4k: An analog I/O 64 x 64 visual microprocessor chip with 7-bit analog accuracy INTERNATIONAL JOURNAL OF CIRCUIT THEORY AND APPLICATIONS
Artículo2002 Architectural and basic circuit considerations for a flexible 128 x 128 mixed-signal SIMD vision chip ANALOG INTEGRATED CIRCUITS AND SIGNAL PROCESSING
Ponencia2002 Bio-inspired analog parallel array processor chip with programmable spatio-temporal dynamics Proceedings - IEEE International Symposium on Circuits and Systems
Ponencia2002 Bio-inspired analog VLSI design realizes programmable complex spatio-temporal dynamics on a single chip DESIGN, AUTOMATION AND TEST IN EUROPE CONFERENCE AND EXHIBITION, 2002 PROCEEDINGS
Ponencia2002 CMOS realization of a 2-layer CNN universal machine chip CELLULAR NEURAL NETWORKS AND THEIR APPLICATIONS
Ponencia2002 Mismatch-induced tradeoffs and scalability of mixed-signal vision chips Proceedings - IEEE International Symposium on Circuits and Systems
Artículo2002 Ultra-High Frame Rate Focal Plane Image Sensor and Processor IEEE SENSORS JOURNAL
Ponencia2001 ACE16K: An advanced focal-plane analog programmable array processor European Solid-State Circuits Conference
Ponencia2000 CNN technology in action PROCEEDINGS OF THE 2000 6TH IEEE INTERNATIONAL WORKSHOP ON CELLULAR NEURAL NETWORKS AND THEIR APPLICATIONS (CNNA 2000)
Ponencia2000 Experimental demonstration of real-time image-processing using a VLSI analog programmable array processor APPLICATIONS OF ARTIFICIAL NEURAL NETWORKS IN IMAGE PROCESSING V
Ponencia2000 Implementation of non-linear templates using a decomposition technique by a 0.5 μm CMOS CNN universal chip Proceedings - IEEE International Symposium on Circuits and Systems
Ponencia2000 Object oriented image segmentation on the CNNUC3 chip PROCEEDINGS OF THE 2000 6TH IEEE INTERNATIONAL WORKSHOP ON CELLULAR NEURAL NETWORKS AND THEIR APPLICATIONS (CNNA 2000)
Ponencia2000 Programmable resolution imager for imaging applications SENSORS AND CAMERA SYSTEMS FOR SCIENTIFIC, INDUSTRIAL AND DIGITAL PHOTOGRAPHY APPLICATIONS
Ponencia2000 Realization of non-linear templates using the CNNUC3 prototype PROCEEDINGS OF THE 2000 6TH IEEE INTERNATIONAL WORKSHOP ON CELLULAR NEURAL NETWORKS AND THEIR APPLICATIONS (CNNA 2000)
Ponencia2000 Structure reconfigurability of the CNNUC3 for robust template operation PROCEEDINGS OF THE 2000 6TH IEEE INTERNATIONAL WORKSHOP ON CELLULAR NEURAL NETWORKS AND THEIR APPLICATIONS (CNNA 2000)
Ponencia2000 The CNNUC3: An analog I/O 64 x 64 CNN universal machine chip prototype with 7-bit analog accuracy PROCEEDINGS OF THE 2000 6TH IEEE INTERNATIONAL WORKSHOP ON CELLULAR NEURAL NETWORKS AND THEIR APPLICATIONS (CNNA 2000)
Ponencia1999 A 0.5μm CMOS 106transistors analog programmable array processor for real-time image processing European Solid-State Circuits Conference
Ponencia1999 A 0.5μm CMOS analog RAM chip for real-time video processing European Solid-State Circuits Conference
Artículo1999 A programmable imager for very high speed cellular signal processing JOURNAL OF VLSI SIGNAL PROCESSING SYSTEMS FOR SIGNAL IMAGE AND VIDEO TECHNOLOGY
Artículo1999 An 0.5-mu m CMOS Analog Random Access Memory Chip for TeraOPS Speed Multimedia Video Processing IEEE TRANSACTIONS ON MULTIMEDIA
Ponencia1999 CNNUC3: A mixed-signal 64 x 64 CNN Universal Chip PROCEEDINGS OF THE SEVENTH INTERNATIONAL CONFERENCE ON MICROELECTRONICS FOR NEURAL, FUZZY AND BIO-INSPIRED SYSTEMS, MICORNEURO'99
Artículo1999 MOST-based design and scaling of synaptic interconnections in VLSI analog array processing CNN chips JOURNAL OF VLSI SIGNAL PROCESSING SYSTEMS FOR SIGNAL IMAGE AND VIDEO TECHNOLOGY
Artículo1999 SIRENA: A CAD environment for behavioural modelling and simulation of VLSI cellular neural network chips INTERNATIONAL JOURNAL OF CIRCUIT THEORY AND APPLICATIONS
Ponencia1998 0.5 μm CMOS CNN analog random access memory chip for massive image processing Proceedings of the IEEE International Workshop on Cellular Neural Networks and their Applications
Ponencia1998 A 64 × 64 CNN universal chip with analog and digital I/O Proceedings of the IEEE International Conference on Electronics, Circuits, and Systems
Ponencia1998 Challenges in mixed-signal IC design of CNN chips in submicron CMOS CNNA 98 - 1998 FIFTH IEEE INTERNATIONAL WORKSHOP ON CELLULAR NEURAL NETWORKS AND THEIR APPLICATIONS - PROCEEDINGS
Ponencia1998 Electro-optical measurement system for the DC characterization of visible detectors for CMOS compatible CNN vision chips CNNA 98 - 1998 FIFTH IEEE INTERNATIONAL WORKSHOP ON CELLULAR NEURAL NETWORKS AND THEIR APPLICATIONS - PROCEEDINGS
Artículo1998 Electrooptical measurement system for the DC characterization of visible detectors for CMOS-compatible vision chips IEEE TRANSACTIONS ON INSTRUMENTATION AND MEASUREMENT
Ponencia1998 Four-quadrant one-transistor-synapse for high-density CNN implementations CNNA 98 - 1998 FIFTH IEEE INTERNATIONAL WORKSHOP ON CELLULAR NEURAL NETWORKS AND THEIR APPLICATIONS - PROCEEDINGS
Artículo1997 A 0.8-mu m CMOS two-dimensional programmable mixed-signal focal-plane array processor with on-chip binary imaging and instructions storage IEEE JOURNAL OF SOLID-STATE CIRCUITS
Ponencia1997 Design of a programmable mixed-signal CMOS image-processing chip in 0.8μm CMOS Proceedings - IEEE International Symposium on Circuits and Systems
Ponencia1997 One-transistor-synapse strategy for electrically-programmable massively-parallel analog array processors IEEE-CAS Region 8 Workshop on Analog and Mixed IC Design, Proceedings
Ponencia1997 Some design trade-offs for large CNN chips using small-size transistors ISCAS '97 - PROCEEDINGS OF 1997 IEEE INTERNATIONAL SYMPOSIUM ON CIRCUITS AND SYSTEMS, VOLS I - IV
Artículo1996 A CNN universal chip in CMOS technology INTERNATIONAL JOURNAL OF CIRCUIT THEORY AND APPLICATIONS
Artículo1996 A VLSI-oriented continuous-time CNN model INTERNATIONAL JOURNAL OF CIRCUIT THEORY AND APPLICATIONS
Ponencia1996 Hybrid-control of synapse circuits for programmable cellular neural networks ISCAS 96: 1996 IEEE INTERNATIONAL SYMPOSIUM ON CIRCUITS AND SYSTEMS - CIRCUITS AND SYSTEMS CONNECTING THE WORLD, VOL 3
Ponencia1996 Mixed-signal CNN array chips for image processing ADVANCED FOCAL PLANE ARRAYS AND ELECTRONIC CAMERAS
Ponencia1995 Realization of a CNN universal chip in CMOS technology 1995 IEEE INTERNATIONAL SYMPOSIUM ON CIRCUITS AND SYSTEMS, VOLS 1-3
Ponencia1994 A continuous-time cellular neural network chip for direction-selectable connected component detection with optical image acquisition Proceedings of the 4th International Conference on Microelectronics for Neural Networks and Fuzzy Systems, ICMNN 1994
Artículo1994 CMOS optical-sensor array with high-output current levels and automatic signal-range centring ELECTRONICS LETTERS
Ponencia1994 CNN universal chip in CMOS technology Proceedings of the IEEE International Workshop on Cellular Neural Networks and their Applications
Ponencia1994 Convergence and stability of the FSR CNN model Proceedings of the IEEE International Workshop on Cellular Neural Networks and their Applications
Ponencia1994 Design of CNN universal chips: Trends and obstacles Proceedings of the IEEE International Workshop on Cellular Neural Networks and their Applications
Ponencia1994 SIRENA: A simulation environment for CNNs Proceedings of the IEEE International Workshop on Cellular Neural Networks and their Applications
Artículo1994 Smart-pixel cellular neural networks in analog current-mode cmos technology IEEE JOURNAL OF SOLID-STATE CIRCUITS
Artículo1994 Tunable feedthrough cancellation in switched-current circuits ELECTRONICS LETTERS
Ponencia1994 Weight-control strategy for programmable CNN chips Proceedings of the IEEE International Workshop on Cellular Neural Networks and their Applications
Ponencia1993 A modified dummy-switch technique for tunable feedthrough cancellation in switched-current circuits European Solid-State Circuits Conference
Ponencia1993 An analog design technique for smart-pixel CMOS chips European Solid-State Circuits Conference
Artículo1993 Current-mode techniques for the implementation of continuous-time and discrete-time cellular neural networks IEEE TRANSACTIONS ON CIRCUITS AND SYSTEMS II-ANALOG AND DIGITAL SIGNAL PROCESSING
Ponencia1993 Model for VLSI implementation of CNN image processing chips using current-mode techniques Proceedings - IEEE International Symposium on Circuits and Systems
Artículo1993 Programabilidad en redes neuronales celulares VIII Congreso Diseño de Circuitos Integrados: Málaga, 9 al 11 de noviembre de 1993
Artículo1993 Una técnica analógica para el diseño de circuitos integrados CMOS de "pixel" inteligente VIII Congreso Diseño de Circuitos Integrados: Málaga, 9 al 11 de noviembre de 1993
Letter1992 A chaotic switched-capacitor circuit for 1/f noise generation IEEE TRANSACTIONS ON CIRCUITS AND SYSTEMS I-FUNDAMENTAL THEORY AND APPLICATIONS
Ponencia1992 An adaptive scheme for feedthrough cancellation in switched-current techniques PROCEEDINGS OF THE 35TH MIDWEST SYMPOSIUM ON CIRCUITS AND SYSTEMS, VOLS 1 AND 2
Ponencia1992 Analog VLSI implementation of cellular neural networks Proceedings - 2nd International Workshop on Cellular Neural Networks and their Applications, CNNA 1992
Artículo1992 Autocorrección del error de inyección de carga en circuitos de modo de corriente conmutada VII Congreso de Diseño de Circuitos Integrados: 3, 4 y 5 de noviembre de 1992, Toledo, España : actas
Ponencia1992 Design and testing issues in current-mode Cellular Neural Networks Proceedings - 2nd International Workshop on Cellular Neural Networks and their Applications, CNNA 1992
Ponencia1992 Switched-current techniques for image processing Cellular Neural Networks in MOS VLSI Proceedings - IEEE International Symposium on Circuits and Systems
Artículo1992 Técnicas de corrientes en conmutación para la implementación de redes neuronales celulares en tiempo discreto VII Congreso de Diseño de Circuitos Integrados: 3, 4 y 5 de noviembre de 1992, Toledo, España : actas
Artículo1991 Switched-capacitor broad-band noise generator for CMOS VLSI ELECTRONICS LETTERS
Ponencia1990 Design of an analog/digital truly random number generator Proceedings - IEEE International Symposium on Circuits and Systems
Ponencia1989 Application of chaotic switched-capacitor circuits for random number generation IEE Conference Publication
Ponencia1989 Application of piecewise-linear switched-capacitor circuits for random number generation Midwest Symposium on Circuits and Systems

Tesis dirigidas/tutorizadas:1
Fecha lectura Título Rol
15/12/2016 DISEÑO CMOS DE SISTEMAS DE FRONT-END PARA INSTRUMENTACIÓN AMBIENTAL EN MARTE Director/a

Proyectos de Investigación

Fecha de inicio Fecha de fin Rol Denominación Agencia financiadora
01/01/2015 31/12/2016 Responsable Microelectrónica de Espacio para Instrumentación Ambiental en Marte (ESP2014-54256-C4-4-R) Ministerio de Economía y Competitividad (Nacional)
01/01/2012 31/12/2013 Responsable Diseño de Circuitos Integrados de Señal Mixta para Aplicaciones Espaciales (AYA2011-29967-C05-05) Ministerio de Ciencia e Innovación (Nacional)
01/01/2010 31/12/2012 Responsable Diseño y testado de ASICs para el espacio para la misión "MEIGA-MetNet Precursor" (AYA2009-14212-C05-04) Ministerio de Ciencia e Innovación (Nacional)
01/01/2019 31/12/2021 Responsable Calibración del Sensor de Viento de Meda y ASIC del Sensor de Viento Esférico (RTI2018-098728-B-C32) Ministerio de Ciencia, Innovación y Universidades (Nacional)
01/01/2009 30/04/2010 Responsable Diseño y testado de asics para el espacio para la misión a Marte "Meiga-Metnet Precursor" (AYA2008-06420-C04-02) Ministerio de Ciencia e Innovación (Nacional)
30/12/2016 29/12/2019 Responsable Microelectrónica para Instrumentación Espacial: ASIC del Sensor de Viento de Meda (ESP2016-79612-C3-3-R) Ministerio de Economía y Competitividad (Nacional)

Contratos

Fecha de inicio Fecha de fin Rol Denominación Agencia financiadora
03/07/2001 31/12/2001 Investigador/a Microelectrónica: tecnología, diseño y test (DICTAM - IST1999 -12342) (OG-017/02) Consejo Superior de Investigaciones Científicas (Nacional)
17/07/1998 31/12/1998 Investigador/a MICROELECTRÓNICA: TECNOLOGÍA, DISEÑO Y TEST (OG-008/99)
03/07/2001 31/12/2001 Investigador/a Microelectrónica: tecnología, diseño y test (ESPRIT 31103 - INSPECT) (OG-016/02) Consejo Superior de Investigaciones Científicas (Nacional)
04/01/2005 31/03/2005 Investigador/a Microelectrónica: tecnología, diseño y test (OG-121/05) Consejo Superior de Investigaciones Científicas (CSIC) (Nacional)
17/07/1998 31/12/1998 Investigador/a MICROELECTRÓNICA: TECNOLOGÍA, DISEÑO Y TEST (OG-005/99)
22/07/2003 31/12/2003 Investigador/a Microelectrónica: tecnología, diseño y test (OG-081/04) Consejo Superior de Investigaciones Científicas (CSIC) (Nacional)
17/07/1998 31/12/1998 Investigador/a MICROELECTRÓNICA: TECNOLOGÍA, DISEÑO Y TEST (OG-007/99)
27/09/2002 31/12/2002 Investigador/a Microelectrónica: tecnología, diseño y test (OG-034/03) Consejo Superior de Investigaciones Científicas (CSIC) (Nacional)
17/07/1998 31/12/1998 Investigador/a MICROELECTRÓNICA: TECNOLOGÍA, DISEÑO Y TEST (OG-006/99)